Title :
Design and implementation of high performance array multipliers for digital circuits
Author :
Srivastava, Prashant ; Vishant, V. ; Singh, R.K. ; Nagaria, R.K.
Author_Institution :
Dept. of Electron. & Commun. Eng., Motilal Nehru Nat. Inst. of Technol., Allahabad, India
Abstract :
In this paper, two low power and high speed array multipliers have been proposed. The proposed multiplier-1 provides approximately 24% reduction in power consumption and 56% reduction in delay as compared with those of conventional array multiplier. The proposed multiplier-2 is based on new hybrid adder which provides approximately 17% reduction in power consumption and 5% reduction in delay. All designs proposed in this paper have been implemented using UMC 0.18μm CMOS technology. The implementation results show that all new designs have superior performance (reduction in the propagation delay and power consumption) compared to previously proposed designs.
Keywords :
CMOS integrated circuits; digital circuits; multiplying circuits; CMOS technology; digital circuit; high speed array multipliers; power consumption; Adders; Arrays; Delays; Hybrid power systems; Logic gates; Power demand; Transistors; Differential Cascode Voltage Switch ( DCVS); Power Consumption; Power Delay Product (PDP); Propagation Delay;
Conference_Titel :
Engineering and Systems (SCES), 2013 Students Conference on
Conference_Location :
Allahabad
Print_ISBN :
978-1-4673-5628-2
DOI :
10.1109/SCES.2013.6547571