Processor with 4.9-μs break-even time in power gating using crystalline In-Ga-Zn-oxide transistor

Author

Kobayashi, Hideo ; Kato, Kazuhiko ; Ohmaru, T. ; Yoneda, Satoshi ; Nishijima, T. ; Maeda, Shigenobu ; Ohshima, K. ; Tamura, H. ; Tomatsu, H. ; Atsumi, T. ; Shionoiri, Y. ; Machashi, Y. ; Koyama, Jun ; Yamazaki, Shumpei

Author_Institution

Semicond. Energy Lab. Co., Ltd., Atsugi, Japan

fYear

2013

fDate

17-19 April 2013

Firstpage

1

Lastpage

3

Abstract

A processor having a power management unit (PMU) and an 8-bit CPU including flip-flops with shadow memories is fabricated by 0.5-μm Si and 0.8-μm c-axis-aligned crystalline In-Ga-Zn-oxide (CAAC-IGZO) technology. The shadow memories hold data without power supply utilizing low off-state current of CAAC-IGZO FETs. A break-even time (BET) of 4.9μs has been obtained. Good scalability of the processor in writing data to shadow memories and in area (5.7% overhead or less) is also confirmed through simulation and layout, based on flip-flops using 30-nm Si FETs combined with 0.3-μm CAAC-IGZO FETs which show good electronic characteristics and no overhead in area.

Keywords

field effect memory circuits; field effect transistors; flip-flops; gallium; indium; microprocessor chips; silicon; zinc; FET; In-Ga-Zn; Si; break-even time; field effect transistors; flip-flops; microprocessor chips; power gating; power management unit; shadow memories; size 0.3 mum; size 0.5 mum; size 0.8 mum; size 30 nm; time 4.9 mus; word length 8 bit; Capacitors; Field effect transistors; Flip-flops; Phasor measurement units; Power supplies; Silicon; Writing; CAAC IGZO; break even time; crystalline IGZO; normally off computing and shadow memory; power gating;

fLanguage

English

Publisher

ieee

Conference_Titel

Cool Chips XVI (COOL Chips), 2013 IEEE

Conference_Location

Yokohama

Print_ISBN

978-1-4673-5780-7

Electronic_ISBN

978-1-4673-5781-4

Type

conf

DOI

10.1109/CoolChips.2013.6547913

Filename

6547913