Title :
Finite Element Analysis and Experiment Validation of Highly Reliable Silicon and Glass Interposers-to-Printed Wiring Board SMT Interconnections
Author :
Xian Qin ; Kumbhat, Nitesh ; Raj, P. Markondeya ; Sundaram, Venky ; Tummala, Rao
Author_Institution :
Packaging Res. Center, Georgia Inst. of Technol., Atlanta, GA, USA
Abstract :
Interposers that support high input/output density are becoming critical for system miniaturization and high performance. Silicon and glass are emerging as the primary candidates for such high-density interposers, due to their outstanding dimensional stability, which enables layer-to-layer wiring with small vias. However, silicon and glass have very low coefficient of thermal expansion (CTE), 3-8 ppm/°C, compared with organic printed wiring board (PWB), which has a CTE of 12-18 ppm/°C. The large CTE mismatch between interposer and board raises reliability concern with the ball grid array interconnections. In this paper, compliant dielectric build-up layers laminated on silicon and glass interposers are explored as stress buffers to reduce the strain accumulated in solder interconnections. Finite element method was used to analyze the thermo-mechanical reliability of the interconnections, and predict the fatigue life of solder joints. Three types of low-CTE interposer materials were studied, low-CTE glass (3 ppm/°C), high-CTE glass (8 ppm/°C), and silicon (2.7 ppm/°C). Test vehicles with the above three interposers at a size of 7.2 mm × 7.2 mm with 25-μm-thick polymer stress buffers laminated on both sides were fabricated, and assembled on organic FR-4 boards using Sn96.5Ag3Cu0.5 solder. The reliability of the solder interconnections, with the three different test vehicles, was studied using thermal cycling test from -40 °C to 125 °C. The high-CTE glass sample was observed to survive 1800 thermal cycles before the first failure was detected in one of the corner joints. Experimental results of fatigue life of interconnections agreed well with finite element modeling results, and reliable interconnections between low-CTE interposer and organic PWB using stress buffers were demonstrated. Based on the validated model, parametric study was conducted to explore the influence of geometry and material p- operties of interposer on the thermo-mechanical reliability of the solder interconnections, as a guideline for interconnection design of similar interposers.
Keywords :
ball grid arrays; elemental semiconductors; fatigue testing; finite element analysis; glass; printed circuit interconnections; printed circuits; semiconductor device reliability; silicon; silver compounds; solders; surface mount technology; thermal expansion; tin compounds; CTE; Si; Sn96.5Ag3Cu0.5; ball grid array interconnections; coefficient of thermal expansion; dielectric build-up layers; fatigue life; finite element analysis; interposers-to-printed wiring board SMT interconnections; layer-to-layer wiring; organic FR-4 boards; polymer stress buffers; size 25 mum; size 7.2 mm; solder interconnections; temperature -40 degC to 125 degC; thermal cycling test; thermomechanical reliability; Fatigue; Glass; Reliability; Silicon; Strain; Stress; Vehicles; Compliant dielectric; finite element method; model validation; reliability test; thin silicon or glass interposer; thin silicon or glass interposer.;
Journal_Title :
Components, Packaging and Manufacturing Technology, IEEE Transactions on
DOI :
10.1109/TCPMT.2013.2296780