DocumentCode :
612997
Title :
Path selection based on static timing analysis considering input necessary assignments
Author :
Bo Yao ; Sinha, Aloka ; Pomeranz, Irith
Author_Institution :
Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
fYear :
2013
fDate :
April 29 2013-May 2 2013
Firstpage :
1
Lastpage :
6
Abstract :
We describe a procedure based on an existing static timing analysis tool for selecting path delay faults to target during test generation. The use of an existing static timing analysis tool ensures that a state-of-the-art process can be used for estimating path delays. However, static timing analysis, by itself, can be inaccurate as it does not take into consideration conditions that are necessary for detecting path delay faults. In the proposed method, these conditions are captured as what are called input necessary assignments, which static timing analysis tools are able to use. By providing the static timing analysis process with the input necessary assignments for a selected path, the static timing analysis process can estimate the delay of the path more accurately. It can also identify additional paths whose delays are at least as high as those of the selected paths. Thus, feeding back the input necessary assignments to the static timing analysis process enhances the correlation between static timing analysis and actual timing of tests on silicon. The result is a set of potentially detectable path delay faults associated with critical paths based on more accurate estimates of the path delays that can be exhibited by a test set, compared with the set that would be obtained by static timing analysis alone.
Keywords :
circuit testing; delay circuits; delay estimation; elemental semiconductors; fault diagnosis; silicon; timing circuits; Si; input necessary assignment; path delay estimation; path delay fault detection; path delay fault selection; static timing analysis tool; test generation; Circuit faults; Correlation; Delays; Fault diagnosis; Integrated circuit modeling; Inverters; Delay testing; input necessary assignments; path selection; static timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Test Symposium (VTS), 2013 IEEE 31st
Conference_Location :
Berkeley, CA
ISSN :
1093-0167
Print_ISBN :
978-1-4673-5542-1
Type :
conf
DOI :
10.1109/VTS.2013.6548902
Filename :
6548902
Link To Document :
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