Title :
An IDDQ BIST approach to characterize phase-locked loop parameters
Author :
Maltabas, S. ; Ekekon, O.K. ; Kulovic, K. ; Meixner, A. ; Margala, Martin
Author_Institution :
Univ. of Massachusetts Lowell, Lowell, MA, USA
fDate :
April 29 2013-May 2 2013
Abstract :
In this work, a new IDDQ built-in self-test (BIST) solution is proposed to provide accurate on-chip current measurements for phase-locked loops (PLLs) found in deep-submicron system-on-chip (SoC) products. The proposed method characterizes PLL loop parameters to increase test quality with minimum additional test time and 4.5% accuracy in IBM 65 nm technology. A self-correction mechanism accompanies the proposed BIST to recover performance variations resulting from excessive process variation found in high-volume manufacturing (HVM). The proposed IDDQ BIST circuit´s performance is evaluated in silicon using 0.18μm technology and achieves 2% accuracy with only 1.7% additional PLL area overhead. Extensions to other analog mixed signal circuit blocks should be possible.
Keywords :
built-in self test; electric current measurement; mixed analogue-digital integrated circuits; phase locked loops; system-on-chip; BIST; HVM; IDDQ BIST approach; IDDQ built-in self-test; IBM technology; PLL; PLL loop parameter; SoC product; analog mixed signal circuit blocks; deep-submicron system-on-chip products; excessive process variation; high-volume manufacturing; on-chip current measurements; phase-locked loop parameter; self-correction mechanism; size 0.18 mum; size 65 nm; test quality; Built-in self-test; Clocks; Current measurement; Jitter; Phase locked loops; Resistors; System-on-chip; AMS BIST; IDDQ testing; PLL testability;
Conference_Titel :
VLSI Test Symposium (VTS), 2013 IEEE 31st
Conference_Location :
Berkeley, CA
Print_ISBN :
978-1-4673-5542-1
DOI :
10.1109/VTS.2013.6548911
