Special session 12B: Panel post-silicon validation & test in huge variance era

At the 1999 ITC, Pat Gelsinger from Intel delivered an important keynote address where he outlined the need for a low-pin count tester with lower performance pin electronics to meet the stringent test cost requirements of a billion transistor machine. At the 2009 ITC, engineers from AMD came forward with an I/O test solution that is believed to meet the Intel challenge using a cash-resident self-testing strategy combined with an external low-pin count tester. How can we drive major challenges to post-silicon validation and in huge variance era? Technology scaling enables us to trade off amplitude resolution for time resolution. Accordingly, both internal and external tests, some of which use low-pin count testers, are also shifting from voltage centric tests to timing centric tests. How can time resolution be used to push the timing centric tests beyond current limitations? How can spatial resolution be realized to enhance yields in terms of both die-to-die variations and within-die variations? What is necessary to provide robust on-chip solutions subject to huge variations, which may be combined with an external low-pin count tester?