Efficient automated speedpath debugging

Speedpath diagnosis is one of the major challenges in designing high-performance Very-Large-Scale Integrated (VLSI) circuits due to timing variations caused by process variations and environmental effects. In this paper, an efficient approach to automate speedpath debugging is presented. The approach relies on converting the timing behavior of a circuit and its corresponding timing variations into functional domain. Afterwards, a SAT-based debug engine is utilized to extract potential failing speedpaths. The experimental results on ISCAS´85 and ISCAS´89 benchmark suites show that our approach achieves a 63% decrease in the size of model resulting in 54% decrease in the debugging time compared to previous work while having a high diagnosis accuracy.