DocumentCode :
613534
Title :
Design of stochastic Viterbi decoders for convolutional codes
Author :
Te-Hsuan Chen ; Hayes, John P.
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., Univ. of Michigan, Ann Arbor, MI, USA
fYear :
2013
fDate :
8-10 April 2013
Firstpage :
66
Lastpage :
71
Abstract :
The Viterbi algorithm is widely used to decode convolutional codes. We present an unconventional approach to Viterbi decoder design based on stochastic computing (SC) which represents data by random bit-streams that can be interpreted as probabilities. Stochastic circuits allow many decoding functions to be implemented by simple hardware; e.g., multi-bit multiplication can be realized by an AND gate. SC is also highly error-tolerant since a soft error (bit-flip) has little impact on a SC number´s value. It also allows decoding precision to be traded for decoding speed. We design two SC-based Viterbi decoders and also a hybrid binary-SC design; the latter uses SC for arithmetic calculations, but not for storing numbers. The proposed designs are compared with a binary (non-SC) decoder using a standard (7, 1/2) convolutional code. The SC designs are found to be more tolerant of soft errors in the decoder than the binary design, and more capable of supporting some useful trade-offs among area cost, data rate, precision, and bit-error rate.
Keywords :
Viterbi decoding; convolutional codes; logic design; logic gates; stochastic processes; AND gate; SC number value; SC-based Viterbi decoders; Viterbi algorithm; area cost; binary decoder; bit-error rate; bit-flip; data rate; decoding functions; decoding precision; decoding speed; hybrid binary-SC design; multibit multiplication; probabilities; random bit-streams; soft error; soft errors; standard convolutional code; stochastic Viterbi decoder design; stochastic circuits; stochastic computing; Clocks; Convolutional codes; Decoding; Noise; Shift registers; Viterbi algorithm; Convolutional codes; Stochastic computing; Stochastic logic design; Viterbi decoders;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2013 IEEE 16th International Symposium on
Conference_Location :
Karlovy Vary
Print_ISBN :
978-1-4673-6135-4
Electronic_ISBN :
978-1-4673-6134-7
Type :
conf
DOI :
10.1109/DDECS.2013.6549790
Filename :
6549790
Link To Document :
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