A GHz full-division-range programmable divider with output duty-cycle improved

This work presents a full-division-range programmable frequency divider with a 50% duty-cycle output. The proposed programmable frequency divider includes a programmable counter (PC) and duty-cycle improved circuit (DCIC) to achieve a full-division-range, low-area, and close-to-50% duty-cycle output from an input clock with an arbitrary duty cycle. A chip was fabricated using a 0.18-μm standard CMOS process with a 1.8-V power supply. The measurement results show that the proposed programmable frequency divider can operate from 1 MHz to 1 GHz, and the division ratio ranges from 1 to 63. When the input divisor is 20, the input clock is 700 MHz, the input duty-cycle is 20%, and output duty-cycle is 50.4%. The total power consumption of the proposed programmable frequency divider is only 0.62 mW at 700 MHz, and the active die area is only 0.125 × 0.05 mm².