An area efficient hardware architecture design for H.264/AVC intra prediction reconstruction path based on partial reconfiguration

The H.264/AVC standard supports intra prediction in order to reduce spatial redundancy in the video frame. The intra prediction process for one macro block requires reconstructing the left and top neighbor macro blocks where the reconstruction path includes a number of processing units such as integer transform, quantization, inverse quantization and inverse integer transform. In order to meet the real time performance constraints of different video standards, a high throughput through this path is necessary. In this paper we propose architecture for real time implementation of the reconstruction path used in the H.264/AVC where the hardware is designed to be used as part of a complete H.264 video coding system. Each processing block executes in a single clock cycle for all calculations required for one 4×4 block. In order to minimize area cost while maintaining the performance, dynamic partial reconfiguration is employed in the quantization and inverse quantization modules such that an area - efficient solution is found without impairing the throughput.