Power analysis methodology for secure circuits

Author

Gomina, Kamil ; Rigaud, J. ; Gendrier, P. ; Candelier, P. ; Tria, Assia

Author_Institution

STMicroelectron., Crolles, France

fYear

2013

fDate

8-10 April 2013

Firstpage

102

Lastpage

107

Abstract

A study on power consumption of a digital synchronous circuit in advanced CMOS technology is performed. These technologies target low power applications allowing accurate power analysis. A model of power signature is developed to identify data related consumption using current consumption and power delivery network capacitance at design phase. In addition to digital power characterization tool, device junction capacitance is extracted and used to provide an accurate power signature. Simulations are compared to experimental traces on a synchronous digital circuit to validate the approach. This model can also be used for complex analog/digital circuit. Finally two countermeasures masking and decoupling capacitance flattening are analyzed with our methodology in early design phase allowing to anticipate silicon tests.

Keywords

CMOS digital integrated circuits; elemental semiconductors; integrated circuit design; integrated circuit testing; low-power electronics; silicon; Si; advanced CMOS technology; circuit security; complex analog-digital circuit; current consumption; decoupling capacitance flattening; design phase; device junction capacitance; digital power characterization tool; digital synchronous circuit; low-power applications; masking; power analysis methodology; power consumption; power delivery network capacitance; power signature model; silicon tests; Hardware design languages; Logic gates; Silicon;

fLanguage

English

Publisher

ieee

Conference_Titel

Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2013 IEEE 16th International Symposium on

Conference_Location

Karlovy Vary

Print_ISBN

978-1-4673-6135-4

Electronic_ISBN

978-1-4673-6134-7

Type

conf

DOI

10.1109/DDECS.2013.6549797

Filename

6549797