Title :
Digital methods of offset compensation in 90nm CMOS operational amplifiers
Author :
Nagy, G. ; Arbet, D. ; Stopjakova, V.
Author_Institution :
Dept. of IC Design & Test, Slovak Univ. of Technol., Bratislava, Slovakia
Abstract :
This paper deals with comparison of two discrete methods for digital trimming of the input offset voltage in operation amplifiers designed in 90nm CMOS technology. Two different topologies based on the binary weighed ladder, one using successive approximation register (SAR) and the other employing a simple counter, were compared. Furthermore, a correction circuit was proposed and used to form the mean offset voltage and increase the probability that its value after trimming process will be near zero. Finally, achieved results and improvements are discussed.
Keywords :
CMOS analogue integrated circuits; approximation theory; compensation; integrated circuit design; ladder networks; operational amplifiers; probability; CMOS operational amplifier; SAR; binary weighed ladder; correction circuit; digital method; digital trimming process; discrete method; input mean offset voltage; offset compensation; probability; size 90 nm; successive approximation register; CMOS integrated circuits; CMOS technology; Histograms; Network topology; Radiation detectors; Standards; Topology; 90nm CMOS; analog circuits; digital calibration; input offset compensation; operational amplifier;
Conference_Titel :
Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2013 IEEE 16th International Symposium on
Conference_Location :
Karlovy Vary
Print_ISBN :
978-1-4673-6135-4
Electronic_ISBN :
978-1-4673-6134-7
DOI :
10.1109/DDECS.2013.6549802
