Title :
Numerical method for DC fault analysis simplification and simulation time reduction
Author :
Brenkus, Juraj ; Stopjakova, V. ; Gyepes, G.
Author_Institution :
Dept. of IC Design & Test, Slovak Univ. of Technol., Bratislava, Slovakia
Abstract :
This paper presents a numerical approach to DC fault analysis of analog circuits that improves the total computational time and reduces the total complexity of such analysis. The reduction is achieved by utilization of calculus that can substitute conventional simulations and thus, significantly reducing computational time. A detailed description of the approach including its mathematical background is presented. Accuracy and time efficiency are demonstrated on a test circuit.
Keywords :
analogue circuits; circuit reliability; circuit simulation; fault diagnosis; numerical analysis; DC fault analysis simplification; analog circuits; mathematical background; numerical method; simulation time reduction; test circuit; time efficiency; Analytical models; Circuit faults; Computational modeling; Integrated circuit modeling; Mathematical model; Numerical models; Resistance; analog circuit; fault analysis; resistance; simulation; test;
Conference_Titel :
Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2013 IEEE 16th International Symposium on
Conference_Location :
Karlovy Vary
Print_ISBN :
978-1-4673-6135-4
Electronic_ISBN :
978-1-4673-6134-7
DOI :
10.1109/DDECS.2013.6549811
