Yield-oriented energy and performance model for subthreshold circuits with Vth variations

We present a method to analyze the minimum energy point of subthreshold logic circuits, taking into account the effect of gate sizing and the transistor threshold voltage variability. With respect to a target yield, technology and circuit parameters this method can give estimates of optimal choices for supply voltage and gate sizing, as well as serve as a tool for design space exploration and technology comparision. We apply this modeling technique to a 90 nm technology, and draw contour plots of the design space. These plots indicate that larger than minimum size gates may be required to achieve minimum energy operation in the subthreshold domain. Optimal voltages range from about 350 mV to 550 mV, depending on the switching activity of the circuit. In the appendix we also give a method of approximating the sum of iid. log-normal RVs, which is used to analyze the timing performance of gates in series.