DocumentCode
613572
Title
Assertion based verification using PSL-like properties in Haskell
Author
Uchevler, B.N. ; Svarstad, K.
Author_Institution
Dept. of Electron. & Telecommun., Norwegian Univ. of Sci. & Technol., Trondheim, Norway
fYear
2013
fDate
8-10 April 2013
Firstpage
254
Lastpage
257
Abstract
With the increasing complexity of designs, the verification costs grow considerably. Using Assertion Based Verification with assertions implemented on real hardware, can speed up the verification process. Property Specification Language is one of the common standards for describing formal properties and specifications of a design. We implemented a subset of PSL operations in Haskell in this work. A functional programming language like Haskell can appear as an advantageous choice for formal verification and high-level descriptions. We use the implemented PSL operators to set up different synthesizable PSL properties. The implemented PSL operators are tested on an FPGA for an AMBA AHB-based system which is also implemented in Haskell.
Keywords
field programmable gate arrays; formal verification; high level languages; AMBA AHB-based system; FPGA; Haskell; PSL-like properties; assertion based verification; formal properties; formal verification; functional programming language; high-level descriptions; property specification language; real hardware; verification process; Clocks; Field programmable gate arrays; Functional programming; Hardware; Hardware design languages; Monitoring; Semantics;
fLanguage
English
Publisher
ieee
Conference_Titel
Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2013 IEEE 16th International Symposium on
Conference_Location
Karlovy Vary
Print_ISBN
978-1-4673-6135-4
Electronic_ISBN
978-1-4673-6134-7
Type
conf
DOI
10.1109/DDECS.2013.6549828
Filename
6549828
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