Redundancy algorithm for embedded memories with block-based architecture

Built-in self-repair (BISR) is widely used to repair embedded memories within system on a chip (SoC) designs to improve their yield. One key component of the BISR circuit responsible for allocating redundancies is the redundancy analysis (RA) algorithm. One of the most important parameters used to evaluate RA algorithms is repair rate (the ratio of the number of the repaired memories to the number of faulty memories). In most BISR designs, redundancies are used on the row/column level. Some approaches target the block-based architecture where both memories and redundancies are divided into several blocks. Thus, allocation can be done on the block level and is more effective in terms of repair rate. These approaches, however, cannot guarantee optimal repair rate. In this paper, we propose a redundancy analysis algorithm for bit-oriented memories with block-based redundancy architecture with optimal repair rate.