Title :
Fault-Tolerant Reconfigurable Low-Power pseudoRandom number Generator
Author :
Petrovic, V. ; Stamenkovic, Z. ; Stojcev, M. ; Nikolic, T. ; Jovanovic, G.
Author_Institution :
Syst. Design, IHP, Frankfurt (Oder), Germany
Abstract :
The article describes a Fault-Tolerant Reconfigurable Low-power pseudoRandom number Generator (FT_RLRG) which integrates both Fibonacci and Galois LFSRs into a single hardware core. The design of FT_RLRG is of practical interest in testing triple modular fault-tolerant systems in the presence of single event upsets (SEUs), especially in case when the system is SRAM based. The main idea is to design a low-cost and low-power hardware structure which is able to adapt to any standard operating at high-speed with different polynomials (currently up to 32nd order). Proposed FT_RLRG design was implemented as an ASIC in the IHP´s 130 nm CMOS technology.
Keywords :
CMOS integrated circuits; SRAM chips; application specific integrated circuits; fault tolerance; integrated circuit design; low-power electronics; radiation hardening (electronics); random number generation; ASIC; FT-RLRG design; Fibonacci LFSR; Galois LFSR; IHP CMOS technology; SEU; SRAM based system; fault-tolerant reconfigurable low-power pseudorandom number generator; low-power hardware structure; polynomials; single event upsets; single hardware core; size 130 nm; triple modular fault-tolerant system testing; Circuit faults; Fault tolerance; Fault tolerant systems; Hardware; Polynomials; Registers; Standards; LFSR; fault tolerance; low power; pseudorandom number generator; reconfiguration;
Conference_Titel :
Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2013 IEEE 16th International Symposium on
Conference_Location :
Karlovy Vary
Print_ISBN :
978-1-4673-6135-4
Electronic_ISBN :
978-1-4673-6134-7
DOI :
10.1109/DDECS.2013.6549834
