Title :
MBIST for LEON3 processor core cache
Author :
Kincel, A. ; Balaz, M.
Author_Institution :
Inst. of Inf., Bratislava, Slovakia
Abstract :
The paper presents a testing method for cache memories of specific processor core. The proposed method uses specially designed scalable MBIST architecture to perform all desired test operations and is independent of memory cache type. The designed MBIST architecture allows performing tests even during processor´s functional mode which is the main advantage over software-based solutions. Achieved results are demonstrated by test execution time.
Keywords :
built-in self test; cache storage; microprocessor chips; LEON3 processor core cache; cache memories; memory built-in self-test; processor functional mode; scalable MBIST architecture; software-based solutions; Arrays; Cache memory; Circuit faults; Generators; Process control; Radiation detectors; Testing; BIST; LEON; MATS++; MBIST; cache test; processor test;
Conference_Titel :
Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2013 IEEE 16th International Symposium on
Conference_Location :
Karlovy Vary
Print_ISBN :
978-1-4673-6135-4
Electronic_ISBN :
978-1-4673-6134-7
DOI :
10.1109/DDECS.2013.6549836
