Techniques to reduce run time in cell timing characterization flow

Library characterization is an essential part of digital design flow and the success of integrated circuits; however, with the growing complexity in cell models, characterization of a large digital cell library has increased the number of simulation jobs by 1000x in recent years. Recently users can find library files sized in gigabytes instead of megabytes, which requires a system that runs reliably and rapidly. Moreover, in nanometre technologies, design teams require more corners and complex models that can take 10 times longer to characterize than previous technologies. Without correctly and fast characterized libraries, an entire design project and millions of dollars in design and fabrication time may be at risk. Accurate library characterization is the cornerstone of successful digital implementation. Synthesis, place-and-route, verification and sign-off tools rely on detailed model libraries to accurately represent the timing, noise and power performance of digital and memory designs. The complexity of these libraries dramatically increases as designs migrate to lower process nodes, on which process variability calls for fast characterization on multiple corners. This process repeats with every new device model version from the foundry. Low-power SoC design further complicates this process by introducing complex cells such as multi-voltage level, shifters and retention logic, which must be accurately characterized to ensure effective digital implementation across multiple power domains. This paper addresses the limitations of current cell characterization flow from run time perspective, and proposes new techniques to reduce the total run time. It is concluded with a brief description of the simulation results based on proposed technique using a real digital library in a 130 nm technology PDK.