A new simple RC modeling for on-chip interconnects with its applications to buffer insertion

A new improved RC modeling for on-chip interconnects derived from pi-configuration of AWE-Based RLC model is presented. A platform utilized to generate all-possible T- and pi configurations of RC, RLC and RLCG models using GAM, TPN, and AWE methods is proposed. 18 different RC, RLC, and RLCG models are generated based on this platform. The pi-configuration of AWE-RLC model provides the best performance. This model is mapped into an improved RC model to preserve the accuracy of the RLC model while keeping the simplicity of the RC model. As compared with conventional RC model, the simulation results of interconnect´s delay with buffer insertion show that the proposed RC model improves the delay by 20.5%, reduces the number of required buffers by 24%, and the buffer sizes by 32%.