A low-power low-delay dispersion comparator for high-speed level-crossing ADCs

This paper presents a new technique for a low-power low delay dispersion comparator for low-cost high-speed level-crossing Analog-to-Digital Converters (LC-ADCs). Only three transistors, representing a variable driving-current block (VDCB), have been added to the conventional comparator circuit. The VDCB works to control the charging behavior of the difference amplifier´ output node such that it is supplied with a current that is inversely proportional with the difference between the positive and negative inputs (overdrive voltage). The modification incurs small area overhead and low power consumption compared with the previous works. The proposed circuit is implemented in 130nm technology. The simulation results show that the overdrive-related propagation delay dispersion of the proposed technique is 23% of its counterpart in the conventional comparator for an input frequency up to 600MHz. The active area of the technique 140.2 μm2 and the power consumption is 227μW at 200MHz. The proposed circuit is also design and simulated using 45nm technology. The simulation results came in the same direction, which implies that the proposed circuit is scalable.