Advanced litho-cluster control via integrated in-chip metrology

The high-end semiconductor lithography requirements for overlay and focus control in near-future ITRS nodes are at subnanometer level. This development is extremely challenging for the metrology precision and accuracy, as scaling down to the sub-angstrom level is required for this. On top of the extreme metrology requirements, direct feed-back control of the lithographic steps is needed to meet the future node requirements. Integrated metrology with in-chip measurements, advanced sampling and control-mechanism (using the highest order of correction possible with scanner interface today), are a few of such technologies considered in this publication.