DocumentCode
614976
Title
Optimizing inspection recipe by using virtual inspector virtual analyzer and failure bitmap
Author
Jang, Roma ; Dongchul Ihm ; Byoungho Lee ; Poh Boon Yong ; Simon, Gael ; Jian Wu ; Lynch, Graham ; Sivaraman, Gangadharan ; Chang Ho Lee
Author_Institution
Semicond. R&D Center, Samsung Electron. Co. Ltd., Dongdan, South Korea
fYear
2013
fDate
14-16 May 2013
Firstpage
262
Lastpage
264
Abstract
This paper presents a novel systematic methodology to identify yield limiting killer defects by using KLA-Tencor´s wafer inspection tools, Klarity Bitmap software and VIVA (Virtual Inspector Virtual Analyzer). This methodology covers two approaches: optimize inspection recipe through short-loop wafers from ADI (After-Develop Inspection) to AEI (After-Etch Inspection); re-optimize inspection recipe by using bitmap failures from Klarity Bitmap as hot spots to VIVA. The results of this study demonstrated that the chipmakers can potentially shorten the learning cycle for identifying killer defects by using this method.
Keywords
circuit optimisation; failure analysis; inspection; integrated circuit yield; ADI; AEI; KLA Tencor; Klarity Bitmap software; VIVA; after develop inspection; after etch inspection; bitmap failures; inspection recipe optimization; learning cycle; short loop wafers; systematic methodology; virtual inspector virtual analyzer; wafer inspection tools; yield limiting killer defects; Failure analysis; Inspection; Limiting; Optimization; Profitability; Software; Systematics; BitPower; DOI; Klarity; Overlay; VIVA; bitmap; defect inspection; hot spot; recipe optimization; yield learning;
fLanguage
English
Publisher
ieee
Conference_Titel
Advanced Semiconductor Manufacturing Conference (ASMC), 2013 24th Annual SEMI
Conference_Location
Saratoga Springs, NY
ISSN
1078-8743
Print_ISBN
978-1-4673-5006-8
Type
conf
DOI
10.1109/ASMC.2013.6552815
Filename
6552815
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