Suppression of Flicker Noise Up-Conversion in a 65-nm CMOS VCO in the 3.0-to-3.6 GHz Band

Flicker noise up-conversion in voltage-biased oscillators can be effectively suppressed by inserting resistances in series to the drain of the transconductor MOSFETs. This solution avoids the degradation of the start-up margin and the adoption of area-demanding resonant filters with proper tuning. This paper presents a detailed theoretical analysis of 1/f noise up-conversion and quantitatively addresses the impact of two major contributions, namely the Groszkowski effect and the loop delay caused by stray capacitances at the drain node of the transistors. A simple flow for the design of an oscillator with suppressed flicker noise up-conversion is presented which is based on first-order closed-form formulas. Finally , theoretical estimates are compared to experimental results on a 65-nm CMOS VCO covering the 3.0-3.6 GHz band.