Code block segmentation hardware architecture for LTE-Advanced

A very efficient algorithm and hardware architecture for code block segmentation used on LTE-Advanced channel coding physical layer (PHY) is presented in this paper. Code block segmentation is a generic procedure which is commonly applied before turbo encoding. Its main function is to fragment a large transport block into smaller code blocks. This approach reduces memory requirements of the turbo code interleaver, without compromising its coding gain, since turbo encoder improves its performance as the size of the code block increases. The current work presents not only an optimized procedure with reduced computational complexity, but also an architecture with very low resource count, regarding ASIC or FPGA implementations, performing at a maximum frequency of 351 MHz on a FPGA architecture.