• DocumentCode
    61677
  • Title

    Trellis-Based Extended Min-Sum Algorithm for Non-Binary LDPC Codes and its Hardware Structure

  • Author

    Erbao Li ; Declercq, David ; Gunnam, K.

  • Author_Institution
    ETIS Lab., Univ. Cergy-Pontoise, Cergy-Pontoise, France
  • Volume
    61
  • Issue
    7
  • fYear
    2013
  • fDate
    Jul-13
  • Firstpage
    2600
  • Lastpage
    2611
  • Abstract
    In this paper, we present an improvement and a new implementation of a simplified decoding algorithm for non-binary low density parity-check codes (NB-LDPC) in Galois fields GF(q). The base algorithm that we use is the Extended Min-Sum (EMS) algorithm, which has been widely studied in the recent literature, and has been shown to approach the performance of the belief propagation (BP) algorithm, with limited complexity. In our work, we propose a new way to compute modified configuration sets, using a trellis representation of incoming messages to check nodes. We call our modification of the EMS algorithm trellis-EMS (T-EMS). In the T-EMS, the algorithm operates directly on the deviation space by considering a trellis built from differential messages, which serves as a new reliability measure to sort the configurations. We show that this new trellis representation reduces the computational complexity, without any performance degradation. In addition, we show that our modifications of the algorithm allows to greatly reduce the decoding latency, by using a larger degree of hardware parallelization.
  • Keywords
    Galois fields; computational complexity; decoding; parity check codes; reliability; trellis codes; BP algorithm; EMS algorithm; Galois fields; NB-LDPC; T-EMS; belief propagation algorithm; check nodes; computational complexity; hardware parallelization; hardware structure; incoming messages; nonbinary LDPC codes; nonbinary low density parity-check codes; reliability; simplified decoding; trellis representation; trellis-EMS; trellis-based extended min-sum algorithm; Complexity theory; Decoding; Equations; Hardware; Parity check codes; Reliability; Vectors; Extended min-sum; hardware implementation; layered decoder; message-passing decoder; non-binary LDPC; trellis representation;
  • fLanguage
    English
  • Journal_Title
    Communications, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0090-6778
  • Type

    jour

  • DOI
    10.1109/TCOMM.2013.050813.120489
  • Filename
    6516166