Efficient concurrent BIST with comparator-based response analyzer

Advances of semiconductor technology have brought impressive performance improvements in Very Large Scale Integrated (VLSI) circuits. Nonetheless, they have also led to increasing rates of faults occurrence. In order to circumvent these faults in on-line and off-line BIST, a novel input vector monitoring concurrent BIST scheme termed pre-Computed test Set Monitoring and Real Time Comparing (CSMRTC) exploiting comparator-based response analyzer is presented in this paper. Experimental results on ISCAS´85 benchmark circuits show that, compared to previously proposed schemes, the CSMRTC scheme has great improvements on both the hardware overhead (H/O) and the concurrent test latency (CTL), and makes some circuits detectable, which cannot be detected by previous methods because of the unacceptable CTL and H/O.