A unique technique for reducing the effects of hot-carrier induced degradations in CMOS bistable circuits for fault tolerant VLSI design

The dominant degradation mechanisms in submicron CMOS devices have been identified as hot-carrier induced stress and may affect performance and reliability of VLSI circuits. The physical mechanisms responsible for the generation of the hot-carriers and its effects on device parameters must be clearly understood in order to model the degradation effects on circuit parameters forming part of the VLSI circuit. Using substrate current as a monitor and employing circuit level simulations over a typical operating cycle, the hot-carrier stress on MOS devices and its degradation effects have been modeled. Our investigations have shown that the transistors in a VLSI circuit do not receive the same amount of hot-carrier stress when operated under dynamic operating conditions. It was seen that the stress levels on the transistors during dynamic operation is a complex function of its location, terminal voltages, current magnitudes and duty cycle. The circuit performance may degrade considerably or the circuit itself may fail due to the stress levels experienced by one or more critical devices in the circuit. Using the technique described, it is possible to identity those critical devices having higher levels of stress and it is possible to apply design improvements which could reduce the stress and hence improve reliability. We present an advanced design method which was used to reduce stress levels of identified critical devices in a standard CMOS circuit thereby improving circuit reliability and performance. A life-time model was used to predict improvements in expected operational life of the circuit after design improvements. This method could be extended to other types of circuits and subsystems used in VLSI circuits.