Analysis of place and route algorithm for field programmable gate array (FPGA)

This paper focuses on the algorithm which can be very efficient for the purpose to minimize the delays introduced in the circuit because of placement and routing. Placing and routing operations are performed when an FPGA device is used for implementation. The delay introduced by logic block and the delay introduced by interconnection can be analyzed by the use of efficient place and route algorithm. The placement algorithms use a set of fixed modules and the netlist describing the connections between the various modules as their input. The output of the algorithms is the best possible position for each module based on various cost functions, which further reduces the cost and power and increases the performances.