Low voltage DCI based low power VLSI circuit implementation on FPGA

Author

Pandey, Bishwajeet ; Kumar, Ravindra

Author_Institution

VLSI Design Lab., Indian Inst. of Inf. Technol. & Manage., Gwalior, Gwalior, India

fYear

2013

fDate

11-12 April 2013

Firstpage

128

Lastpage

131

Abstract

In this paper, we study the effect of using digitally controlled impedance IO Standard in memory interface design in terms of power consumption. In this work, we achieved 50% dynamic power reduction at 1.5V output driver voltage, 35.2% dynamic power reduction at 1.8V output driver voltage in comparison to 2.5V output driver voltage in DCI based IO standard implementation on input or output port in target design. Target device XC6VLX75TFF484-1 is a Virtex-6 FPGA of -1 speed grade and 484 pins is used for implementation of this design. Target Design is RAM-UART memory interface. XPower 13.4 is used for power analysis of our low power memory interface design. ISim is simulator to generate waveform. Planahead is used for design, synthesis and implementation.

Keywords

VLSI; digital control; field programmable gate arrays; low-power electronics; ISim; Planahead; RAM UART memory interface; Virtex-6 FPGA; XPower; digitally controlled impedance IO standard; dynamic power reduction; low power memory interface design; low voltage DCI based low power VLSI circuit; output driver voltage; power analysis; power consumption; simulator; voltage 1.5 V; voltage 1.8 V; voltage 2.5 V; waveform; Clocks; Field programmable gate arrays; Impedance; Power demand; Random access memory; Standards; System-on-chip; Digitally Controlled Impedance; Dynamic Power Reduction; FPGA; Low Power; Memory Interface;

fLanguage

English

Publisher

ieee

Conference_Titel

Information & Communication Technologies (ICT), 2013 IEEE Conference on

Conference_Location

JeJu Island

Print_ISBN

978-1-4673-5759-3

Type

conf

DOI

10.1109/CICT.2013.6558076

Filename

6558076