DocumentCode
618320
Title
Spur reduction technique for integer-N frequency synthesizer
Author
Musheer, Tharannum ; Chandramani, P.
Author_Institution
Dept. of Electron. & Commun., SSN Coll. of Eng., Kalavakkam, India
fYear
2013
fDate
11-12 April 2013
Firstpage
414
Lastpage
419
Abstract
Modelling a PLL based 40MHz integer-N frequency synthesizer to identify and eliminate the reference spurs. The macro-model has a gain margin of 6.64dB and a phase margin of 43.1°, ensuring the stability of the closed loop system with a settling time of 3.85μsec. A notch-type comb filter was modelled to eliminate the periodically occurring reference spurs observed at 20MHz and 60MHz.
Keywords
closed loop systems; frequency synthesizers; notch filters; phase locked loops; PLL; closed loop system stability; frequency 20 MHz; frequency 40 MHz; frequency 60 MHz; gain 6.64 dB; gain margin; integer-N frequency synthesizer; macromodel; notch-type comb filter; phase margin; spur reduction technique; time 3.85 mus; Finite impulse response filters; Frequency conversion; Frequency synthesizers; IIR filters; Phase locked loops; Phase noise; Voltage-controlled oscillators; PLL; VCO; frequency synthesizer; phase noise; spurs;
fLanguage
English
Publisher
ieee
Conference_Titel
Information & Communication Technologies (ICT), 2013 IEEE Conference on
Conference_Location
JeJu Island
Print_ISBN
978-1-4673-5759-3
Type
conf
DOI
10.1109/CICT.2013.6558131
Filename
6558131
Link To Document