A Novel Quasi-3-D Interface-Trapped-Charge-Induced Threshold Voltage Model for Quadruple-Gate MOSFETs, Including Equivalent Number of Gates

With the effects of interface trapped charges on the flat-band voltage, we report a novel quasi-3-D interface-trapped-charge-induced threshold voltage model for quadruple-gate (QG) MOSFETs based on the scaling equation including equivalent number of gates. It is found that a thin gate oxide and a small ratio of damaged region to channel region are required to reduce the threshold voltage degradation by the trapped charges. In addition, the damaged device with a thick silicon film suffers the small threshold voltage degradation by the negative trapped charges. In comparison with other multiple-gate MOSFETs, the QG MOSFET is better than double-gate and triple-gate MOSFETs in suppressing the threshold voltage degradation by the positive trapped charges. The model can be used to explore the hot-carrier-induced threshold voltage of the QG MOSFET for its memory device application.