Area and power efficient network on chip router architecture

In System on Chip, buses and point to point links are used as a communication infrastructure between one IP to another, but these cannot provide efficient interconnect from performance point of view. So NoC architecture was proposed to provide communication in multiprocessor SoC and overcome the limitations. This paper has implemented a 5-port 32-bit and 64-bit router architecture using wormhole routing technique for 2D-mesh network by using simple deterministic algorithm, flow control and decoding mechanism. In this router, 2 types of crossbar are used named as multiplexer and tri-state buffer matrix for efficient design. Comparisons of area and power are done for these router designs using ASIC tool flow in Cadence using TSMC 90nm and 180nm process technologies. Simulation results are performed in Cadence NC simulator. It is demonstrated that multiplexer router design is more efficient than a matrix router design as area and power increases for matrix design while using same port-width.