FPGA based implementation of quantization and its inverse for H.264 codec

Author

Mukherjee, Rohan ; Keyur, S. ; Sandeep, E. ; Chakrabarti, Indrajit ; Chakrabarti, S. Sengupta

Author_Institution

Dept. of Electron. & Electr. Commun. Eng., Indian Inst. of Technol., Kharagpur, Kharagpur, India

fYear

2013

fDate

11-12 April 2013

Firstpage

986

Lastpage

989

Abstract

H.264, which is the most advanced video compression standard till date, includes novel algorithms for quantization and inverse quantization processes. In this paper, a new hardware architecture exclusively based on combinational logic is proposed for the quantizer and inverse quantizer blocks for real-time video processing. Implemented in Xilinx14.1, Virtex-5 technology, the proposed architectures for quantizer and its inverse have demonstrated combinational path delays of 12.38 ns and 10.79 ns respectively.

Keywords

combinatorial mathematics; data compression; field programmable gate arrays; formal logic; video coding; FPGA based implementation; H.264 codec; Virtex-5 technology; Xilinx14.1; combinational logic; combinational path delays; hardware architecture; inverse quantization processes; inverse quantizer blocks; real-time video processing; video compression standard; Arrays; Field programmable gate arrays; Image reconstruction; Quantization (signal); Standards; Transforms; FPGA; Forward Quantization; H.264; Inverse Quantization;

fLanguage

English

Publisher

ieee

Conference_Titel

Information & Communication Technologies (ICT), 2013 IEEE Conference on

Conference_Location

JeJu Island

Print_ISBN

978-1-4673-5759-3

Type

conf

DOI

10.1109/CICT.2013.6558240

Filename

6558240