Multiple bit error correction for high data rate aerospace applications

With the continuous decrease in the minimum feature size and increase in the chip density due to technology scaling on-chip memories are becoming increasingly susceptible to multi-bit soft errors due to single or multiple event upsets caused by environmental factors such as cosmic rays, neutrons particles. The increase in multi-bit errors could lead to higher risk of data corruption and even catastrophic disasters in aerospace applications. Traditionally the memories have been protected from soft errors using error detection/correction codes. The traditional Hamming code with SEC-DED capability cannot address these type of errors. It is possible to use powerful non-binary BCH codes such as Reed-Solomon code to address multiple bit errors, However, it could take several cycles of latency to complete such algorithms and run at relatively slow speed. We investigate the possibility of using Reed Muller (RM) codes to address multiple bit errors in. high speed on board aerospace applications in this paper. Comparison with traditional techniques shows improved speed power performance. Specifically with its importance in applications as a 3 bit error correcting, self dual code a RM(2, 5) of dimension 16 and length 32 is implemented in a flash based FPGA, which is much more resistant to Single Event Upsets(SEUs) in comparison to SRAM based FPGAs for onboard applications.