7-T Single End and 8-T differential dual-port SRAM memory cells

The advantages of simultaneous read and write operations for dual-port SRAM memory cells are well known. In this paper two configurations of dual-port 8-Transistor Differential (8T-D) and 7-Transistor Single End SRAM cells are presented. The benefits of power-delay product and power dissipation are verified. The goals of low power and high performance control of the full CMOS SRAM can be achieved. The main aim is to reduce the delay and power dissipation with better performance; compared to previous circuits are accomplished by changing the configuration of 8-transistor single-end SRAM cell. The performances of the proposed circuits are examined using Cadence and the model parameters of a 180 nm CMOS process. The simulation results have confirmed that the proposed 8T-D and 7-Transistor SRAM cells can reduce propagation delay and power dissipation compared with the previous designs.