DocumentCode
618640
Title
A robust repair-aware test method for multi-memory
Author
Gang Wang
Author_Institution
Inst. of Comput. Technol., Beijing, China
fYear
2013
fDate
16-18 April 2013
Firstpage
1
Lastpage
6
Abstract
A complex SoC typically consists of numerous of memories in today´s digital systems. This paper presents a test/repair structure based on memory grouping strategy and a revised distributed BIST structure for complex SoC devices. A gated selecting method is added to the distributed BIST structure. Also, it can be used to a robust post repair stage based on BIRA and memory grouping in test flow to improve the test coverage. Simulation results by mathematical method show that the proposed test flow has achieved a significant increase in yield of memories.
Keywords
built-in self test; integrated circuit testing; integrated memory circuits; system-on-chip; BIRA; complex SoC devices; digital systems; gated selecting method; mathematical method; memory grouping strategy; multimemory; revised distributed BIST structure; robust post repair stage; robust repair-aware test method; test-repair structure; Built-in self-test; Circuit faults; Maintenance engineering; Memory management; Power demand; Redundancy; System-on-chip;
fLanguage
English
Publisher
ieee
Conference_Titel
Design, Test, Integration and Packaging of MEMS/MOEMS (DTIP), 2013 Symposium on
Conference_Location
Barcelona
Print_ISBN
978-1-4673-4477-7
Type
conf
Filename
6559425
Link To Document