An AMBA hierarchical shared bus architecture design space exploration method considering pipeline, burst and split transaction

Recently, a design space exploration problem has been raised with an attempt to reduce time and resources for designing an optimal system-on-a-chip (SoC). This research proposes a design space exploration method considering the architectures containing an AMBA shared bus. The AMBA standard bus specification widely used in many SoC industries as an efficient on-chip interconnect. The proposed method explores the architecture candidates containing AMBA shared buses and their parameters. It also estimates the execution time and the area of each architecture. The first experiment has indicated that the area estimation result is different from the logic synthesis result by less than 1 %. The second experiment has demonstrated that the proposed method found 7 Pareto solutions among over 4 billion architectures in the design space in 19 hours.