Hardware amount evaluation of the improved WEP on an FPGA

The spread of smart phones means the traffic capacity stringent of mobile communications. One way of solving the problem of traffic capacity is the use of a Wi-Fi hotspot. The majority of Wi-Fi hotspots are used WEP (Wired Equivalent Privacy) as a cipher. Nevertheless, the method of deciphering WEP has already been clarified. Some deciphering programs can execute deciphering of WEP in several seconds. To solve this problem, an improved WEP has been proposed. The features of the improved WEP are a compatible algorithm with WEP and strengthening of cipher strength. The improved WEP algorithm has been evaluated only on software and has not been implemented on hardware. On the other hand, ciphers for a WiFi LAN are implemented on an FPGA (Field-Programmable Gate Array) as well as a system LSI and is used in various devices. Additionally, it is important that the size of the processing unit is small. In this paper, the improved WEP is implemented on an FPGA. Then, the number of elements and registers of the improved WEP is compared with that of a conventional WEP. As a result, it is shown that hardware amount of the improved WEP hardly increases. Besides, it is proposed that a method to increase the cipher strength of the improved WEP by utilizing the characteristics of an FPGA and wave-pipelining.