Performance Analysis of a Proposed Pre-FEC Structure for a DVB-C2 Receiver

To increase the spectral efficiency of HFC network, the standard of digital video broadcasting for cable systems (DVB-C2) was completed in 2010 and products that support the DVB-C2 is expected to be released within years. Before making products for DVB-C2 receiver, the performance of them should be investigated under various channel conditions first. Thus, we show the performance of the proposed structure for a pre-FEC in DVB-C2 receiver considering the channel model including additive white Gaussian noise (AWGN), a frequency offset, and echo channels to provide information about the implementation of DVB-C2 receiver. Based on the simulation results, we implement the pre-FEC using two field programmable gate arrays (FPGAs) and show the measured symbol error rate (SER) between the transmitted and received quadrature amplitude modulation (QAM) symbols with respect to various symbol timing estimations (STEs) of synchronization (SYNC) and powers of analog-to-digital converter (ADC) input. Because the STE makes the received pilot symbols in preamble rotated and these rotated pilot symbols are used in channel estimation, it affects the channel estimation and SER of pre-FEC. In addition, the channel estimation impaired by the STE causes the received QAM symbols to have biased mean values compared with the transmitted 4096QAM symbols. Since this degrades the performance of pre-FEC, the automatic gain control (AGC) is added after zero-forcing linear equalizer (ZF-LE) to improve the performance of pre-FEC. As the power of ADC input decreases, the SER increases due to the noise enhancement of ZF-LE.