DocumentCode :
619528
Title :
Smart non-default routing for clock power reduction
Author :
Kahng, Andrew ; Seokhyeong Kang ; Hyein Lee
Author_Institution :
ECE, Univ. of California at San Diego, La Jolla, CA, USA
fYear :
2013
fDate :
May 29 2013-June 7 2013
Firstpage :
1
Lastpage :
7
Abstract :
At advanced process nodes, non-default routing rules (NDRs) are integral to clock network synthesis methodologies. NDRs apply wider wire widths and spacings to address electromigration constraints, and to reduce parasitic and delay variations. However, wider wires result in larger driven capacitance and dynamic power. In this work, we quantify the potential for capacitance and power reduction through the application of “smart” NDR (SNDR) that substitute narrower-width NDRs on selected clock network segments, while maintaining skew, slew, delay and EM reliability criteria. We propose a practical methodology to apply smart NDRs in standard clock tree synthesis flows. Our studies with a 32/28nm library and open-source benchmarks confirm substantial (average of 9.2%) clock wire capacitance reduction and an average of 4.9% clock switching power savings over the current fixed-NDR methodology, without loss of QoR in the clock distribution.
Keywords :
benchmark testing; capacitance; clock distribution networks; electromigration; integrated circuit design; network routing; power consumption; switching circuits; EM reliability criteria; QoR; SNDR; advanced process nodes; clock distribution; clock network segments; clock network synthesis methodologies; clock power reduction; clock switching power savings; clock wire capacitance reduction; current fixed-NDR methodology; delay variation reduction; driven capacitance; dynamic power; electromigration constraints; narrower-width NDR; open-source benchmarks; parasitic variation reduction; size 32 nm to 28 nm; smart NDR; smart nondefault routing rules; standard clock tree synthesis flows; wider wire widths; Capacitance; Clocks; Delays; Mathematical model; Optimization; Routing; Wires; Clock Network Optimization; Clock Network Synthesis; Power Minimization;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference (DAC), 2013 50th ACM/EDAC/IEEE
Conference_Location :
Austin, TX
ISSN :
0738-100X
Type :
conf
Filename :
6560684
Link To Document :
بازگشت