Title :
Efficiently tolerating timing violations in pipelined microprocessors
Author :
Chakraborty, Koushik ; Cozzens, Bradley ; Roy, Sandip ; Ancajas, Dean Michael
Author_Institution :
USU Bridge Lab., Utah State Univ., Logan, UT, USA
fDate :
May 29 2013-June 7 2013
Abstract :
Early prediction of an upcoming timing violation presents a tremendous opportunity to mask the performance overhead of tolerating these faults. In this paper, we explore several techniques for optimizing instruction scheduling in an Out-of-Order pipeline, exploiting this new perspective in robust system design. Compared to recently proposed stall based techniques for tolerating predictable timing violations, we demonstrate a massive reduction in performance overhead, while supporting correct execution in faulty environments (64-97% across different benchmarks).
Keywords :
fault tolerance; microprocessor chips; pipeline processing; fault tolerant; instruction scheduling; out-of-order pipeline; pipelined microprocessors; timing violations; Circuit faults; Delays; Engines; Integrated circuit modeling; Pipelines; Processor scheduling; Instruction Scheduling; Path Sensitization; Timing Faults;
Conference_Titel :
Design Automation Conference (DAC), 2013 50th ACM/EDAC/IEEE
Conference_Location :
Austin, TX