DocumentCode
619554
Title
A robust constraint solving framework for multiple constraint sets in Constrained Random Verification
Author
Bo-Han Wu ; Chung-Yang Huang
Author_Institution
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
fYear
2013
fDate
May 29 2013-June 7 2013
Firstpage
1
Lastpage
7
Abstract
To verify system-wide properties on SoC designs in Constrained Random Verification (CRV), the default set of constraints to generate patterns could be overridden frequently through the complex testbench. It usually results in the degradation of pattern generation speed because of low hit-rate problems. In this paper, we propose a technique to preprocess the solution space under each constraint set. Regarding the similarity between constraint sets, the infeasible subspaces under a constraint set help identify the infeasible subspaces under another constraint set. The profiled results under each constraint set are then stored in a distinct range-splitting tree (RS-Tree). These trees accelerate pattern generation under multiple constraint sets and, simultaneously, ensure the produced patterns are evenly-distributed. In our experiments, our framework achieved 10X faster pattern generation speed than a state-of-art tool in average.
Keywords
integrated circuit design; system-on-chip; CRV; RS-tree; SoC designs; complex testbench; constrained random verification; infeasible subspaces; multiple constraint sets; pattern generation speed degradation; range-splitting tree; robust constraint solving framework; system-wide properties; Acceleration; Degradation; Estimation; Inference algorithms; Legged locomotion; Runtime; System-on-chip; Constrained Random Verification (CRV); Functional Verification;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference (DAC), 2013 50th ACM/EDAC/IEEE
Conference_Location
Austin, TX
ISSN
0738-100X
Type
conf
Filename
6560712
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