DocumentCode :
619555
Title :
Simulation knowledge extraction and reuse in constrained random processor verification
Author :
Wen Chen ; Li-Chung Wang ; Bhadra, Jayanta ; Abadir, Magdy
Author_Institution :
Univ. of California - Santa Barbara, Santa Barbara, CA, USA
fYear :
2013
fDate :
May 29 2013-June 7 2013
Firstpage :
1
Lastpage :
6
Abstract :
This work proposes a methodology of knowledge extraction from constrained-random simulation data. Feature-based analysis is employed to extract rules describing the unique properties of novel assembly programs hitting special conditions. The knowledge learned can be reused to guide constrained-random test generation towards uncovered corners. The experiments are conducted based on the verification environment of a commercial processor design, in parallel with the on-going verification efforts. The experimental results show that by leveraging the knowledge extracted from constrained-random simulation, we can improve the test templates to activate the assertions that otherwise are difficult to activate by extensive simulation.
Keywords :
circuit testing; electronic engineering computing; formal verification; knowledge acquisition; learning (artificial intelligence); multiprocessing systems; assembly programs; commercial processor design; constrained random processor verification; constrained-random simulation data; constrained-random test generation; feature-based analysis; knowledge learning; on-going verification efforts; rule extraction; simulation knowledge extraction; Accuracy; Assembly; Feature extraction; Generators; Measurement; Registers; Vectors; Assertion; Coverage; Functional Verification; Rule Learning;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference (DAC), 2013 50th ACM/EDAC/IEEE
Conference_Location :
Austin, TX
ISSN :
0738-100X
Type :
conf
Filename :
6560713
Link To Document :
بازگشت