Time-domain segmentation based massively parallel simulation for ADCs

The great availability of massively parallel computing platforms gives rise a question to the EDA industry-how can this be really helping the productivity of circuit designs. Scalability of traditional parallel methods have shown to be limited as the computational resources keep increasing. In this paper we propose a time-domain segmentation method for massively parallel transistor-level simulation for short-memory circuits. SNDR simulation for ADCs is selected as the application as ADCs are typical short-memory circuits and the SNDR simulation is very time consuming. Experiments with realistic Flash and SAR ADCs demonstrate 64x-78x speed-ups with 100 CPU cores. With minor, yet important modifications, the proposed method can even be applied to simulation of Σ-Δ modulator, which does not satisfy the short-memory condition due to the presence of integrator, and 52x speed-up is observed with 100 CPU cores. The implementation of the proposed method is extremely simple and no modification to simulator is needed.