Title :
Integrated instruction cache analysis and locking in multitasking real-time systems
Author :
Huping Ding ; Yun Liang ; Mitra, Tulika
Author_Institution :
Sch. of Comput., Nat. Univ. of Singapore, Singapore, Singapore
fDate :
May 29 2013-June 7 2013
Abstract :
Cache locking improves timing predictability at the cost of performance. We explore a novel approach that opportunistically employs both cache analysis and locking to enhance schedulability in preemptive multi-tasking real-time systems. The cache is spatially shared among the tasks by statically locking a portion of the cache per task. To overcome the issue of limited cache space per task, we keep a portion of the cache unlocked and let all the tasks use it through time-multiplexing. Compared to locking the entire cache for each task during execution, our approach obviates the cost of reloading locked blocks at preemption. But we require static cache analysis for WCET estimation and cache related preemption delay (CRPD) analysis of the unlocked cache space. We design an algorithm to make appropriate locking decisions through accurate cost-benefit analysis. Experimental results show that our integrated approach leads to substantially improved schedulability results compared to cache analysis and cache locking employed individually.
Keywords :
cache storage; delays; real-time systems; timing; WCET estimation; cache per task; cache related preemption delay analysis; cache space per task; cost-benefit analysis; enhance schedulability; integrated instruction cache analysis; integrated instruction cache locking; locking decision; multitasking real-time systems; preemptive multitasking real-time system; static cache analysis; timing predictability; worst case execution time; Abstracts; Concrete; Delays; Equations; Processor scheduling; Real-time systems; Time factors; CRPD; Cache Locking; Multi-tasking; Real-Time; WCET;
Conference_Titel :
Design Automation Conference (DAC), 2013 50th ACM/EDAC/IEEE
Conference_Location :
Austin, TX