DocumentCode :
619690
Title :
Design of delay line of automatically controlling message cache time
Author :
Liu Hong-bo ; Gao Jun ; Liu Qin-tao ; Ma Jun-kai
Author_Institution :
Electron. Eng. Coll., Naval Univ. of Eng., Wuhan, China
fYear :
2013
fDate :
25-27 May 2013
Firstpage :
195
Lastpage :
197
Abstract :
According to the practical issue that the fixed time relationship between keying signal and message signal of the transmitting terminal is failed to adapt to the every signal channel some transmitters get through, this thesis designs a type of delay line which can automatically control the message cache time. Also, this paper conducts several analyses in numerous aspects, such as design philosophy, hardware frame, logic control, time sequence list, etc. Meanwhile, this kind of delay line is characterized by long time delay, automatic control of delay time and so forth.
Keywords :
delays; signal processing; automatically controlling message cache time; delay line design; design philosophy; fixed time relationship; hardware frame; keying signal; logic control; message signal; signal channel; time sequence list; transmitting terminal; Delay lines; Delays; Frequency control; Frequency conversion; Hardware; Time-frequency analysis; Transmitters; Complex Programmable Logic Device; Delay Line; First-In First-Out;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Control and Decision Conference (CCDC), 2013 25th Chinese
Conference_Location :
Guiyang
Print_ISBN :
978-1-4673-5533-9
Type :
conf
DOI :
10.1109/CCDC.2013.6560919
Filename :
6560919
Link To Document :
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