DocumentCode :
62043
Title :
Resistive Open Faults Detectability Analysis and Implications for Testing Low Power Nanometric ICs
Author :
Mohammadat, Mohamed Tagelsir ; Ali, Noohul Basheer Zain ; Hussin, Fawnizu Azmadi ; Zwolinski, Mark
Author_Institution :
Dept. of Electr. & Electron. Eng., Univ. Teknol. Petronas, Tronoh, Malaysia
Volume :
23
Issue :
3
fYear :
2015
fDate :
Mar-15
Firstpage :
580
Lastpage :
583
Abstract :
Resistive open faults (ROFs) represent common manufacturing defects in IC interconnects and result in delay faults that cause timing failures and reliability risks. The nonmonotonic dependence of ROF-induced delay faults on the supply voltage (VDD) poses a concern as to whether single-VDD testing will suffice for low power nanometric designs. Our analysis shows multi-VDD tests could be required, depending on the test speed. This knowledge can be exploited in small delay fault testing to reduce the chances of test escapes while minimizing cost.
Keywords :
failure analysis; integrated circuit design; integrated circuit reliability; integrated circuit testing; low-power electronics; IC interconnects; ROF-induced delay faults; low power designs; low power nanometric IC testing; reliability risks; resistive open faults detectability analysis; supply voltage; test speed; timing failures; Circuit faults; Delays; Integrated circuit interconnections; Integrated circuit modeling; Resistance; Testing; Very large scale integration; Detectability; low power design; multi- $V_{rm DD}$ test; multi-VDD test; resistive opens; small delay faults; variability;
fLanguage :
English
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
1063-8210
Type :
jour
DOI :
10.1109/TVLSI.2014.2312357
Filename :
6782673
Link To Document :
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