An active disturbance rejection control of induction motor using DSP+FPGA

This paper proposes the active disturbance rejection control (ADRC) architecture aimed to improve the field oriented control (FOC) without speed sensor of a 1-kW induction motor using a digital signal processor (DSP) and a field-programmable gate array (FPGA). The main control algorithms are performed by the DSP, and the simple logical processes are implemented in the FPGA. A basic proportional-integral-differential (PID) controller and the ADRC controller are both implemented on the system. Simulation and experimental results show the advantages and flexibilities of the ADRC architecture for the induction motor control.