DocumentCode :
621060
Title :
Sub-50-nm InGaAs MOSFET with n-InP source on Si substrate
Author :
Kato, Akira ; Kanazawa, Toru ; Uehara, Eiji ; Yonai, Yoshiharu ; Miyamoto, Yutaka
Author_Institution :
Dept. of Phys. Electron., Tokyo Inst. of Technol., Tokyo, Japan
fYear :
2013
fDate :
19-23 May 2013
Firstpage :
1
Lastpage :
2
Abstract :
We demonstrated a sub-50-nm InGaAs 5-nm/InP 5-nm MOSFET with an n-InP source on a Si substrate using a 5-nm Al2O3 dielectric. In the measurement of the fabricated device, the maximum drain current and the peak transconductance at VD = 0.5 V were 0.9 mA/μm and 0.8 mS/m, respectively. The threshold voltage was 0.09 V, and the drain-induced barrier lowering was 378 mV/V. From the channel length dependence, clear suppression of the short channel effect by the 5-nm-thick Al2O3 gate dielectric and the extremely thin body III-V-OI structure was confirmed.
Keywords :
MOSFET; dielectric materials; Al2O3; InGaAs; MOSFET; channel length dependence; drain induced barrier; fabricated device; gate dielectric; maximum drain current; peak transconductance; short channel effect; substrate; threshold voltage; voltage 0.5 V; voltage 0.9 V; Aluminum oxide; Current density; Dielectrics; Indium gallium arsenide; Indium phosphide; Silicon; Substrates;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Indium Phosphide and Related Materials (IPRM), 2013 International Conference on
Conference_Location :
Kobe
ISSN :
1092-8669
Print_ISBN :
978-1-4673-6130-9
Electronic_ISBN :
1092-8669
Type :
conf
DOI :
10.1109/ICIPRM.2013.6562631
Filename :
6562631
Link To Document :
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